The present invention relates to a semiconductor dynamic memory device.
Mass-production of 64K bit dynamic type random access memory devices (DRAMs) has been enabled by the recent development of semiconductor memory devices of high packing density. Furthermore, a 256K bit DRAM has been developed. In this case, in order to prevent an increase in stray capacitance and resistance of word lines and data lines, it is proposed to divide memory cells into a plurality of areas and to provide word lines, data lines and circuits such as sense amplifiers for each memory cell area.
Word lines and data lines in a highly integrated semiconductor memory device conventionally are formed to have narrow width. However, the stray capacitance per unit length of a word line or a data line is not greatly reduced. Furthermore, since the word lines and data lines are made narrow, resistance per unit length of a word line or data line increases. As a result, the delay time of a signal transmitted along the word line or data line is prolonged.
A dynamic random access memory (DRAM) as shown in FIG. 1 includes a memory 2 having a plurality of memory cells arranged in a matrix form, a plurality of pairs of aluminum folded data lines D0-1 and D1-1, D0-2 and D1-2, . . . , and D0-M and D1-M, each of which is connected to memory cells in a given column, word lines W1 to WN of polycrystalline silicon which are each connected to memory cells in a given row, a columm decoder 4 connected to the folded data lines D0-1 and D1-1, . . . , and D0-M and D1-M, a row decoder 6 connected to the word lines W1 to WN, and a sense amplifier circuit 8 connected to the folded data lines D0-1 and D1-1, . . . , and D0-M and D1-M for sensing and amplifying data on the paired data lines. In FIG. 1, a hollow circle indicates a memory cell for storing data and a solid circle or dot indicates a dummy memory cell.
In the DRAM, when data is read out from one of the memory cells connected to the data line D0-1, the data line D0-1 and a selected word line are activated, and the data line D1-1 and the word line WN are also activated. These activated lines select a memory cell and a corresponding dummy cell for determining a potential difference between the data line D0-1 and D1-1. The sense amplifier circuit 8 determines the potentials of the data lines D0-1 and D1-1 according to the initial potential difference therebetween. The potentials on the data lines D0-1 and D1-1 are transmitted to an input/output circuit (not shown).
The DRAM shown in FIG. 2 includes four memory areas 2-1 to 2-4, each of which has the same configuration as the memory 2 shown in FIG. 1, a column decoder 4-1 commonly connected to the memory areas 2-1 and 2-2, a column decoder 4-2 commonly connected to the memory areas 2-3 and 2-4, a row decoder 6-1 commonly connected to the memory areas 2-1 and 2-3, a row decoder 6-2 commonly connected to the memory areas 2-2 and 2-4, and sense amplifier circuits 8-1 to 8-4 connected to the memory areas 2-1 to 2-4, respectively.
In a case where the DRAM shown in FIG. 2 is highly integrated so that the entire chip surface area thereof may be the same as that of the DRAM shown in FIG. 1, and each of the memory areas 2-1 to 2-4 has the same memory capacity as the memory 2 of the DRAM shown in FIG. 1, the DRAM can be formed such that the number of memory cells connected to the word line or data line will be the same, and the length of the word line or data line may be made shorter than that of the word or data line in the DRAM shown in FIG. 1. This shortens the delay time of a signal transmitted through the word line or data line, allowing faster data detection by each of the sense amplifier circuits 8-1 to 8-4 with greater accuracy. However, since the gate oxide film will be thinner due to the high packing density, the stray capacitance of the memory cells of each memory area 2-1 to 2-4 increases, thus adversely affecting the signal transmitted through the word line or data line. Furthermore, in the DRAM shown in FIG. 2, since two column decoders 4-1 and 4-2, two row decoders 6-1 and 6-2, and four sense amplifier circuits 8-1 to 8-4 operate simultaneously when performing read/write operations, the current consumed in charging or discharging the data lines increases greatly. This increase in current consumption raises chip temperature and adversely affects the operation of the DRAM. In particular, such a current has a peak, and changes the internal power source voltage, thereby degrading the operating speed.
FIG. 3 shows a detailed circuit diagram of the basic unit of the DRAM shown in FIG. 1. This circuit includes a sense amplifier 10 having a flip-flop circuit formed of MOS transistors TR1 and TR2 connected to bistable output nodes N1 and N2 and to a control line CL; the data line D0-1, one end of which is connected to the node N1 through a MOS transistor TR3 and the other end of which is connected to a reference voltage terminal VS through MOS transistors TR4 and TR5; and the data line D1-1, one end of which is connected to the node N2 through a MOS transistor TR6 and the other end of which is connected to the reference voltage terminal VS through MOS transistors TR7 and TR8. A MOS transistor TR9 is connected between the data line D0-1 and a power source terminal VD, and a MOS transistor TR10 is connected between the data line D1-1 and the power source terminal VD. A plurality of working memory cells MC0-1, MC0-2, . . . and so on are connected to the data line D0-1, and a plurality of memory cells MC1-1, MC1-2, . . . and so on are connected to the data line D1-1. Each memory cell is formed of a MOS transistor and a capacitor series-connected between the data line D0-1 or D1-1 and the reference voltage terminal VS. A capacitor C0-1 is connected between the reference voltage terminal VS and the junction of the MOS transistors TR4 and TR5. A capacitor C1-1 is connected between the reference voltage terminal VS and the junction of the MOS transistors TR7 and TR8. The MOS transistor TR4 and the capacitor C0-1 constitute a dummy memory cell. The MOS transistor TR7 and the capacitor C1-1 constitute another dummy memory cell. Each of the capacitors C0-1 and C1-1 has a capacitance of 1/2 that of the capacitor of a working memory cell. Furthermore, the data lines D0-1 and D1-1 are connected to input/output data lines DL0 and DL1 through MOS transistors TR11 and TR12, respectively. The MOS transistors TR11 and TR12 are used for column selection.
The read operation of the circuit shown in FIG. 3 will now be described with reference to signal waveforms shown in FIGS. 4A to 4E. Normally, a voltage signal .phi.C at a predetermined potential lever is supplied to the gates of the MOS transistors TR3 and TR6, which serve as resistor elements.
A signal .phi.P shown in FIG. 4B, which is substantially synchronous with a row address strobe signal RAS shown in FIG. 4A and supplied from an outer control circuit (not shown), is supplied to the gates of the MOS transistors TR9 and TR10 from a signal generating circuit (not shown). Then, the MOS transistors TR9 and TR10 are turned ON. Charging currents flow through the respective data lines D0-1 and D1-1 to keep the potential levels thereof equal to that of a power source voltage VD. Thereafter, the signal .phi.P falls substantially syncronously with the row address strobe signal RAS. In this case, a signal .phi.D having the same waveform as the signal .phi.P is applied to the gates of the MOS transistors TR5 and TR8 to turn ON the MOS transistors TR5 and TR8 so as to discharge the capacitors C0-1 and C1-1.
Assume that the memory cell MC0-1 is selected. In this case, a word selection signal shown in FIG. 4C is supplied to the word line W1. Since the memory cell MC0-1 is connected to the data line D0-1, the word line W(N-1) connected to the gate of the MOS transistor TR7, which constitutes the dummy memory cell connected to the data line D1-1, is energized. This changes the voltage level of the data line D0-1 according to the data stored in the memory cell MC0-1; meanwhile the data line D1-1 is set to a predetermined potential. When the memory cell MC0-1 stores, for example, the bit value "1", the potential of the data line D0-1 is made higher than that of the data line D1-1. When the memory cell MC0-1 stores the bit value "0", the potential of the data line D0-1 is made lower than that of the data line D1-1. If a voltage signal .phi.S supplied to the control line CL is set low under these conditions, the conduction states of the MOS transistors TR1 and TR2 are determined in accordance with the difference between the potentials of the data lines D0-1 and D1-1. As a result, the charge on one of the data lines D0-1 and D1-1 is discharged through the one of the MOS transistors TR1 and TR2 which is ON. Thus, a discharging current as shown in FIG. 4E flows. Then, a column selection signal (FIG. 4D) is supplied and voltage signals on the data lines D0-1 and D1-1 are transmitted to an outer circuit (not shown) through the MOS transistors TR11 and TR12 and through the input/output data lines DL0 and DL1.
After the data is read out in the manner described above the word selection signal, shown in FIG. 4C, is set to a low level and the signal .phi.S is set to a high level.
The charging/discharging current shown in FIG. 4E occupies a large percentage of the operating current supplied to the DRAM. It flows when the signal .phi.P rises and the control signal .phi.S falls, as mentioned earlier, and has a sharp current peak. In a 64K bit DRAM, for example, a current peak as large as 100 mA occurs.
If all of a plurality of memory devices arranged on a memory board are operated simultaneously, noise generated by the current peak will be mixed in the power source voltage. This may cause erratic operation.
Furthermore, the current peak may lower the power source voltage or raise a ground potential level in the memory device, thereby causing instability in the operation of the memory device.
In a DRAM having a substrate bias generator, the substrate potential may be varied when the data lines are charged or discharged. This is because of an electrostatic coupling capacitance existing between the data lines and the substrate. The magnitude of the variation is generally about 1 V. If the DRAM is highly densely packed, the variation in the substrate potential increases since the capacitance between the data lines and the substrate increases.
In the conventional DRAM, it is required to refresh all of the memory cells only by the row address data without its most significant bit. Accordingly, in the DRAM shown in FIG. 2, the two memory areas 2-1 and 2-3 having the same row address or the two memory areas 2-2 and 2-4 having the same row address must all be activated at the same time. Even if the row addresses for the memory areas 2-1 and 2-3 are distinguished from those for the memory area 2-2 and 2-4 in terms of the most significant bit, the most significant bit is not included in address data for performing the refreshing operation, and therefore, all of the memory areas 2-1 to 2-4 are activated simultaneously during data refresh. As a result, it is required to operate all of the sense amplifier circuits 8-1 to 8-4 simultaneously, thereby increasing the current comsumption.